module top_ddr4_rw(
	//Differential system clocks and systm reset
	input                              sys_clk_p,
	input                              sys_clk_n,
	input                              sys_rst_n,
	//ddr4 connect
	output                             c0_ddr4_act_n   ,
	output [16:0]                      c0_ddr4_adr     ,
	output [1:0]                       c0_ddr4_ba      ,
	output [0:0]                       c0_ddr4_bg      ,
	output [0:0]                       c0_ddr4_cke     ,
	output [0:0]                       c0_ddr4_odt     ,
	output [0:0]                       c0_ddr4_cs_n    ,
	output [0:0]                       c0_ddr4_ck_t    ,
	output [0:0]                       c0_ddr4_ck_c    ,
	output                             c0_ddr4_reset_n ,
	inout  [1:0]                       c0_ddr4_dm_dbi_n,
	inout  [15:0]                      c0_ddr4_dq      ,
	inout  [1:0]                       c0_ddr4_dqs_c   ,
	inout  [1:0]                       c0_ddr4_dqs_t   ,
	// output init_calib_complete,
    //Read-write correct indicator light
	output [1:0]                       led	
);

//参数
parameter app_addr_rd_min = 29'd0;
parameter app_addr_rd_max = 29'd1024;
parameter rd_bust_len     = 8'd64;//一次突发读的数据量
parameter app_addr_wr_min = 29'd0;
parameter app_addr_wr_max = 29'd1024;
parameter wr_bust_len     = 8'd64;//一次突发写的数据量 


//wire define
wire [15:0] wr_data;
wire [15:0] rd_data;
wire        init_calib_complete;
wire [7:0] wr_fifo_rcount;
wire [7:0] rd_fifo_wcount;
wire app_rd_data_valid;
wire [28:0] c0_ddr4_app_addr;
wire [127:0] rd_fifo_wdata;
clk_wiz_0 u_clk_wiz_0
(
// Clock out ports
.clk_out1(clk_50m), // output clk_out1
// Status and control signals
.reset(~sys_rst_n), // input reset
.locked(), // output locked
// Clock in ports
.clk_in1(ui_clk)); // input clk_in1
//*****************************************************
//**                    main code
//***************************************************** 

ddr4_controler u_ddr4_controler(
    .sys_clk_p       (sys_clk_p), 
    .sys_clk_n       (sys_clk_n), 
    .rst_n           (sys_rst_n),
    //ddr4 connect                
    .c0_ddr4_act_n   (c0_ddr4_act_n   ), 
    .c0_ddr4_adr     (c0_ddr4_adr     ), 
    .c0_ddr4_ba      (c0_ddr4_ba      ), 
    .c0_ddr4_bg      (c0_ddr4_bg      ), 
    .c0_ddr4_cke     (c0_ddr4_cke     ), 
    .c0_ddr4_odt     (c0_ddr4_odt     ), 
    .c0_ddr4_cs_n    (c0_ddr4_cs_n    ), 
    .c0_ddr4_ck_t    (c0_ddr4_ck_t    ), 
    .c0_ddr4_ck_c    (c0_ddr4_ck_c    ), 
    .c0_ddr4_reset_n (c0_ddr4_reset_n ), 
    .c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n), 
    .c0_ddr4_dq      (c0_ddr4_dq      ), 
    .c0_ddr4_dqs_c   (c0_ddr4_dqs_c   ), 
    .c0_ddr4_dqs_t   (c0_ddr4_dqs_t   ),  
    .c0_init_calib_complete(init_calib_complete),
    .c0_ddr4_ui_clk (ui_clk),
    //user connect              
    .app_addr_rd_min (app_addr_rd_min),//ddr4读起始地址 
    .app_addr_rd_max (app_addr_rd_max),//ddr4读结束地址
    .rd_bust_len     (rd_bust_len    ),//一次突发读的数据量 
    .app_addr_wr_min (app_addr_wr_min),//ddr4写起始地址 
    .app_addr_wr_max (app_addr_wr_max),//ddr4写结束地址 
    .wr_bust_len     (wr_bust_len),    //一次突发写的数据量  
    .wr_fifo_wclk    (clk_50m),        //写端FIFO的写数据时钟，一般接数据源的同步时钟
    .rd_fifo_rclk    (clk_50m),        //读端FIFO的读数据时钟，一般接输出设备的数据时钟
    .wr_fifo_wdata   (wr_data),        //写端FIFO的写数据，一般接数据源的数据
    .rd_fifo_rdata   (rd_data),        //读端FIFO的读数据，一般接输出设备的数据通道
    .ddr4_read_valid (1'b1)   ,        //读有效信号，拉高代表可以读取DDR4中的数据
    .wr_fifo_wen     (wr_en)  ,        //写端FIFO的写使能信号
    .rd_fifo_ren     (rd_req) ,         //读端FIFO的读使能信号
    .wr_fifo_rcount (wr_fifo_rcount),
    .rd_fifo_wcount (rd_fifo_wcount),
    .c0_ddr4_app_rd_data_valid (app_rd_data_valid),
    .c0_ddr4_app_addr (c0_ddr4_app_addr), // [28:0] addr
    .rd_fifo_wdata(rd_fifo_wdata) //[127:0] 直接不进fifo读值
);

test_data u_test_data(
    .clk_50m             (clk_50m),      
    .rst_n               (sys_rst_n),
    .init_calib_complete (init_calib_complete) , //ddr4初始化完成信号                
    .rd_data             (rd_data),   
    .rd_req              (rd_req ),  
    .wr_data             (wr_data),      
    .wr_en               (wr_en  ),                                                           
    .error               (error  )                //读写错误标志信号
);   

led_disp u_led_disp(
    .clk_50m            (clk_50m),
    .rst_n              (sys_rst_n),
    //DDR4初始化失败或者读写错误都认为是实验失败
    .error_flag         (error),
    .init_calib_complete(init_calib_complete) , 
    .led                (led) 
);

ila_0 u_ila_0 (
	.clk(clk_50m), // input wire clk


	.probe0(rd_data), // input wire [15:0]  probe0  
	.probe1(app_rd_data_valid), // input wire [0:0]  probe1
    .probe2(wr_fifo_rcount), // input wire [7:0]  probe2 
	.probe3(rd_fifo_wcount), // input wire [7:0]  probe3 
    .probe4(c0_ddr4_app_addr), // input wire [28:0]  probe4 
    .probe5(rd_fifo_wdata) // input wire [127:0]  probe5
);

endmodule